Compiler-based instruction scoreboarding

ABSTRACT

Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to remove unnecessary dependence edges from a data dependency graph, partition the data dependency graph into a plurality of sub-graphs, determine a live range for each of the plurality of sub-graphs, and assign a scoreboard entry to each of the plurality of sub-graphs, wherein sub-graphs which have interfering live ranges are assigned different scoreboard entries. Other embodiments are also disclosed and claimed.

FIELD

The present disclosure generally relates to the field of electronics.More particularly, some embodiments relate to techniques to implementcompiler-based instruction scoreboarding.

BACKGROUND

A register scoreboard is a hardware mechanism commonly used inprocessors such as central processing units (CPUs) and/or graphicsprocessing units (GPUs) to avoid data hazards between instructions thatare executing out of order. A processing unit uses the registerscoreboard to enforce data dependencies by stalling instructions untilthe scoreboard is cleared.

GPUs comprise many small processors, also referred to as execution units(EUs), each of which may have a large register file. Hence, thescoreboard logic may consume an inordinate amount of the GPU's die size.For example, a GPU may contain dozens of EUs, and an EU that includesseven (7) hardware threads, each of which has 128 GRF (General RegisterFile) registers would require scoreboards for 896 registers for each EU.At the same time, all registers may be used as the destination or sourceoperands of the instructions; also the scoreboard must track the statusof multiple registers all at once for the multiple registers accessinstructions in the GPU. All these make the scoreboard logic even morecomplex.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is provided with reference to the accompanyingfigures. In the figures, the left-most digit(s) of a reference numberidentifies the figure in which the reference number first appears. Theuse of the same reference numbers in different figures indicates similaror identical items.

FIGS. 1 and 10 illustrate block diagrams of embodiments of computingsystems, which may be utilized to implement various embodimentsdiscussed herein.

FIGS. 2-6, 8, 13, and 14 illustrate various components of processers inaccordance with some embodiments.

FIG. 7 illustrates graphics core instruction formats, according to someembodiments.

FIGS. 9A and 9B illustrate graphics processor command format andsequence, respectively, according to some embodiments.

FIG. 11 illustrates a diagram of IP core development according to anembodiment.

FIG. 12 illustrates components of a System on Chip (SoC or SOC)integrated circuit, according to an embodiment.

FIGS. 15 and 16 illustrate dependence between instructions in accordancewith some examples.

FIG. 17 is a schematic illustration of a dependence counter inaccordance with some examples.

FIG. 18 is a flow diagram illustrating scoreboarding operationsaccording to some embodiments.

FIG. 19 is a schematic illustration of three types of sub-graphs afterDDG graph simplification.

FIG. 20 is a schematic illustration of a scoreboard allocation process,according to examples.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of various embodiments.However, various embodiments may be practiced without the specificdetails. In other instances, well-known methods, procedures, components,and circuits have not been described in detail so as not to obscure theparticular embodiments. Further, various aspects of embodiments may beperformed using various means, such as integrated semiconductor circuits(“hardware”), computer-readable instructions organized into one or moreprograms (“software”), or some combination of hardware and software. Forthe purposes of this disclosure reference to “logic” shall mean eitherhardware, software, firmware, or some combination thereof.

As mentioned above, the complexity of scoreboard logic can escalaterapidly in multi-processor and/or multi-core environments to the pointat which the scoreboard logic can consume a significant portion of a diefor an integrated circuit. The subject matter described herein addressesthis and other problems by providing techniques to reduce the size andcomplexity of required hardware scoreboard mechanism which may be usedin parallel processing environments such as CPUs and/or GPUs. In someexamples the techniques may be implemented by a compiler and/or by aseparate controller coupled to a compiler. Broadly, the techniquecomprises counter based instruction scoreboarding, simplifying a datadependency graph (DDG), partitioning the simplified DDG into a pluralityof sub-graphs, and determining live ranges for the respective pluralityof sub-graphs. Different scoreboard indices are assigned to sub-graphsfor which there are interferences between their respective live ranges.

In another aspect, the scoreboard may be modified to accommodate datadependencies between instruction operations. In hardware, a scoreboardcounter array is used to track the dependence between instructions. Eachinstruction is extended to include a define index and a use index tospecify the scoreboard item in the array which the instruction willdefine or use. A counter for each scoreboard element is initialized tozero. When an instruction is issued the scoreboard counter specified bythe define index is incremented by one, and when the instructioncompletes the counter specified by the define index is decremented byone. An instruction can be executed only when the counter specified bythe use index is zero.

Further, some embodiments may be applied in computing systems thatinclude one or more processors (e.g., with one or more processor cores),such as those discussed with reference to FIGS. 1-18, including forexample mobile computing devices, e.g., a smartphone, tablet, UMPC(Ultra-Mobile Personal Computer), laptop computer, Ultrabook™ computingdevice, wearable devices (such as a smart watch or smart glasses), etc.

System Overview

FIG. 1 is a block diagram of a processing system 100, according to anembodiment. In various embodiments the system 100 includes one or moreprocessors 102 and one or more graphics processors 108, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 102 or processorcores 107. In one embodiment, the system 100 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 100 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 100 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 100 can also include, be coupled with, or beintegrated within a wearable device, such as a smart watch wearabledevice, smart eyewear device, augmented reality device, or virtualreality device. In some embodiments, data processing system 100 is atelevision or set top box device having one or more processors 102 and agraphical interface generated by one or more graphics processors 108.

In some embodiments, the one or more processors 102 each include one ormore processor cores 107 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 107 is configured to process aspecific instruction set 109. In some embodiments, instruction set 109may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 107 may each process adifferent instruction set 109, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 107may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 102 includes cache memory 104.Depending on the architecture, the processor 102 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 102. In some embodiments, the processor 102 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 107 using knowncache coherency techniques. A register file 106 is additionally includedin processor 102 which may include different types of registers forstoring different types of data (e.g., integer registers, floating pointregisters, status registers, and an instruction pointer register). Someregisters may be general-purpose registers, while other registers may bespecific to the design of the processor 102.

In some embodiments, processor 102 is coupled with a processor bus 110to transmit communication signals such as address, data, or controlsignals between processor 102 and other components in system 100. In oneembodiment the system 100 uses an exemplary ‘hub’ system architecture,including a memory controller hub 116 and an Input Output (I/O)controller hub 130. A memory controller hub 116 facilitatescommunication between a memory device and other components of system100, while an I/O Controller Hub (ICH) 130 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 116 is integrated within the processor.

Memory device 120 can be a dynamic random access memory (DRAM) device, astatic random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 120 can operate as system memory for the system 100, to storedata 122 and instructions 121 for use when the one or more processors102 executes an application or process. Memory controller hub 116 alsocouples with an optional external graphics processor 112, which maycommunicate with the one or more graphics processors 108 in processors102 to perform graphics and media operations.

In some embodiments, ICH 130 enables peripherals to connect to memorydevice 120 and processor 102 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 146, afirmware interface 128, a wireless transceiver 126 (e.g., Wi-Fi,Bluetooth), a data storage device 124 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 140 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 142 connect input devices, suchas keyboard and mouse 144 combinations. A network controller 134 mayalso couple with ICH 130. In some embodiments, a high-performancenetwork controller (not shown) couples with processor bus 110. It willbe appreciated that the system 100 shown is exemplary and not limiting,as other types of data processing systems that are differentlyconfigured may also be used. For example, the I/O controller hub 130 maybe integrated within the one or more processor 102, or the memorycontroller hub 116 and I/O controller hub 130 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 112.

FIG. 2 is a block diagram of an embodiment of a processor 200 having oneor more processor cores 202A-202N, an integrated memory controller 214,and an integrated graphics processor 208. Those elements of FIG. 2having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor200 can include additional cores up to and including additional core202N represented by the dashed lined boxes. Each of processor cores202A-202N includes one or more internal cache units 204A-204N. In someembodiments each processor core also has access to one or more sharedcached units 206.

The internal cache units 204A-204N and shared cache units 206 representa cache memory hierarchy within the processor 200. The cache memoryhierarchy may include at least one level of instruction and data cachewithin each processor core and one or more levels of shared mid-levelcache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or otherlevels of cache, where the highest level of cache before external memoryis classified as the LLC. In some embodiments, cache coherency logicmaintains coherency between the various cache units 206 and 204A-204N.

In some embodiments, processor 200 may also include a set of one or morebus controller units 216 and a system agent core 210. The one or morebus controller units 216 manage a set of peripheral buses, such as oneor more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 210 provides management functionality forthe various processor components. In some embodiments, system agent core210 includes one or more integrated memory controllers 214 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 202A-202Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 210 includes components for coordinating andoperating cores 202A-202N during multi-threaded processing. System agentcore 210 may additionally include a power control unit (PCU), whichincludes logic and components to regulate the power state of processorcores 202A-202N and graphics processor 208.

In some embodiments, processor 200 additionally includes graphicsprocessor 208 to execute graphics processing operations. In someembodiments, the graphics processor 208 couples with the set of sharedcache units 206, and the system agent core 210, including the one ormore integrated memory controllers 214. In some embodiments, a displaycontroller 211 is coupled with the graphics processor 208 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 211 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 208 or system agent core 210.

In some embodiments, a ring based interconnect unit 212 is used tocouple the internal components of the processor 200. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 208 couples with the ring interconnect 212 via an I/O link213.

The exemplary I/O link 213 represents at least one of multiple varietiesof I/O interconnects, including an on package I/O interconnect whichfacilitates communication between various processor components and ahigh-performance embedded memory module 218, such as an eDRAM module. Insome embodiments, each of the processor cores 202A-202N and graphicsprocessor 208 use embedded memory modules 218 as a shared Last LevelCache.

In some embodiments, processor cores 202A-202N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 202A-202N are heterogeneous in terms of instruction setarchitecture (ISA), where one or more of processor cores 202A-202Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 202A-202N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor200 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 3 is a block diagram of a graphics processor 300, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 300 includes amemory interface 314 to access memory. Memory interface 314 can be aninterface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 300 also includes a displaycontroller 302 to drive display output data to a display device 320.Display controller 302 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 300 includesa video codec engine 306 to encode, decode, or transcode media to, from,or between one or more media encoding formats, including, but notlimited to Moving Picture Experts Group (MPEG) formats such as MPEG-2,Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well asthe Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1,and Joint Photographic Experts Group (JPEG) formats such as JPEG, andMotion JPEG (MJPEG) formats.

In some embodiments, graphics processor 300 includes a block imagetransfer (BLIT) engine 304 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 310. In someembodiments, GPE 310 is a compute engine for performing graphicsoperations, including three-dimensional (3D) graphics operations andmedia operations.

In some embodiments, GPE 310 includes a 3D pipeline 312 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 312 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 315.While 3D pipeline 312 can be used to perform media operations, anembodiment of GPE 310 also includes a media pipeline 316 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 316 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 306. In some embodiments, media pipeline 316 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 315. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 315.

In some embodiments, 3D/Media subsystem 315 includes logic for executingthreads spawned by 3D pipeline 312 and media pipeline 316. In oneembodiment, the pipelines send thread execution requests to 3D/Mediasubsystem 315, which includes thread dispatch logic for arbitrating anddispatching the various requests to available thread executionresources. The execution resources include an array of graphicsexecution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 315 includes one or more internal cachesfor thread instructions and data. In some embodiments, the subsystemalso includes shared memory, including registers and addressable memory,to share data between threads and to store output data.

Graphics Processing Engine

FIG. 4 is a block diagram of a graphics processing engine 410 of agraphics processor in accordance with some embodiments. In oneembodiment, the graphics processing engine (GPE) 410 is a version of theGPE 310 shown in FIG. 3. Elements of FIG. 4 having the same referencenumbers (or names) as the elements of any other figure herein canoperate or function in any manner similar to that described elsewhereherein, but are not limited to such. For example, the 3D pipeline 312and media pipeline 316 of FIG. 3 are illustrated. The media pipeline 316is optional in some embodiments of the GPE 410 and may not be explicitlyincluded within the GPE 410. For example, and in at least oneembodiment, a separate media and/or image processor is coupled to theGPE 410.

In some embodiments, GPE 410 couples with or includes a command streamer403, which provides a command stream to the 3D pipeline 312 and/or mediapipelines 316. In some embodiments, command streamer 403 is coupled withmemory, which can be system memory, or one or more of internal cachememory and shared cache memory. In some embodiments, command streamer403 receives commands from the memory and sends the commands to 3Dpipeline 312 and/or media pipeline 316. The commands are directivesfetched from a ring buffer, which stores commands for the 3D pipeline312 and media pipeline 316. In one embodiment, the ring buffer canadditionally include batch command buffers storing batches of multiplecommands. The commands for the 3D pipeline 312 can also includereferences to data stored in memory, such as but not limited to vertexand geometry data for the 3D pipeline 312 and/or image data and memoryobjects for the media pipeline 316. The 3D pipeline 312 and mediapipeline 316 process the commands and data by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to a graphics core array 414.

In various embodiments the 3D pipeline 312 can execute one or moreshader programs, such as vertex shaders, geometry shaders, pixelshaders, fragment shaders, compute shaders, or other shader programs, byprocessing the instructions and dispatching execution threads to thegraphics core array 414. The graphics core array 414 provides a unifiedblock of execution resources. Multi-purpose execution logic (e.g.,execution units) within the graphic core array 414 includes support forvarious 3D API shader languages and can execute multiple simultaneousexecution threads associated with multiple shaders.

In some embodiments the graphics core array 414 also includes executionlogic to perform media functions, such as video and/or image processing.In one embodiment, the execution units additionally includegeneral-purpose logic that is programmable to perform parallel generalpurpose computational operations, in addition to graphics processingoperations. The general purpose logic can perform processing operationsin parallel or in conjunction with general purpose logic within theprocessor core(s) 107 of FIG. 1 or core 202A-202N as in FIG. 2.

Output data generated by threads executing on the graphics core array414 can output data to memory in a unified return buffer (URB) 418. TheURB 418 can store data for multiple threads. In some embodiments the URB418 may be used to send data between different threads executing on thegraphics core array 414. In some embodiments the URB 418 mayadditionally be used for synchronization between threads on the graphicscore array and fixed function logic within the shared function logic420.

In some embodiments, graphics core array 414 is scalable, such that thearray includes a variable number of graphics cores, each having avariable number of execution units based on the target power andperformance level of GPE 410. In one embodiment the execution resourcesare dynamically scalable, such that execution resources may be enabledor disabled as needed.

The graphics core array 414 couples with shared function logic 420 thatincludes multiple resources that are shared between the graphics coresin the graphics core array. The shared functions within the sharedfunction logic 420 are hardware logic units that provide specializedsupplemental functionality to the graphics core array 414. In variousembodiments, shared function logic 420 includes but is not limited tosampler 421, math 422, and inter-thread communication (ITC) 423 logic.Additionally, some embodiments implement one or more cache(s) 425 withinthe shared function logic 420. A shared function is implemented wherethe demand for a given specialized function is insufficient forinclusion within the graphics core array 414. Instead a singleinstantiation of that specialized function is implemented as astand-alone entity in the shared function logic 420 and shared among theexecution resources within the graphics core array 414. The precise setof functions that are shared between the graphics core array 414 andincluded within the graphics core array 414 varies between embodiments.

FIG. 5 is a block diagram of another embodiment of a graphics processor500. Elements of FIG. 5 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 500 includes a ring interconnect502, a pipeline front-end 504, a media engine 537, and graphics cores580A-580N. In some embodiments, ring interconnect 502 couples thegraphics processor to other processing units, including other graphicsprocessors or one or more general-purpose processor cores. In someembodiments, the graphics processor is one of many processors integratedwithin a multi-core processing system.

In some embodiments, graphics processor 500 receives batches of commandsvia ring interconnect 502. The incoming commands are interpreted by acommand streamer 503 in the pipeline front-end 504. In some embodiments,graphics processor 500 includes scalable execution logic to perform 3Dgeometry processing and media processing via the graphics core(s)580A-580N. For 3D geometry processing commands, command streamer 503supplies commands to geometry pipeline 536. For at least some mediaprocessing commands, command streamer 503 supplies the commands to avideo front end 534, which couples with a media engine 537. In someembodiments, media engine 537 includes a Video Quality Engine (VQE) 530for video and image post-processing and a multi-format encode/decode(MFX) 533 engine to provide hardware-accelerated media data encode anddecode. In some embodiments, geometry pipeline 536 and media engine 537each generate execution threads for the thread execution resourcesprovided by at least one graphics core 580A.

In some embodiments, graphics processor 500 includes scalable threadexecution resources featuring modular cores 580A-580N (sometimesreferred to as core slices), each having multiple sub-cores 550A-550N,560A-560N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 500 can have any number of graphicscores 580A through 580N. In some embodiments, graphics processor 500includes a graphics core 580A having at least a first sub-core 550A anda second sub-core 560A. In other embodiments, the graphics processor isa low power processor with a single sub-core (e.g., 550A). In someembodiments, graphics processor 500 includes multiple graphics cores580A-580N, each including a set of first sub-cores 550A-550N and a setof second sub-cores 560A-560N. Each sub-core in the set of firstsub-cores 550A-550N includes at least a first set of execution units552A-552N and media/texture samplers 554A-554N. Each sub-core in the setof second sub-cores 560A-560N includes at least a second set ofexecution units 562A-562N and samplers 564A-564N. In some embodiments,each sub-core 550A-550N, 560A-560N shares a set of shared resources570A-570N. In some embodiments, the shared resources include sharedcache memory and pixel operation logic. Other shared resources may alsobe included in the various embodiments of the graphics processor.

Execution Units

FIG. 6 illustrates thread execution logic 600 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 6 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 600 includes a shaderprocessor 602, a thread dispatcher 604, instruction cache 606, ascalable execution unit array including a plurality of execution units608A-608N, a sampler 610, a data cache 612, and a data port 614. In oneembodiment the scalable execution unit array can dynamically scale byenabling or disabling one or more execution units (e.g., any ofexecution unit 608A, 608B, 608C, 608D, through 608N-1 and 608N) based onthe computational requirements of a workload. In one embodiment theincluded components are interconnected via an interconnect fabric thatlinks to each of the components. In some embodiments, thread executionlogic 600 includes one or more connections to memory, such as systemmemory or cache memory, through one or more of instruction cache 606,data port 614, sampler 610, and execution units 608A-608N. In someembodiments, each execution unit (e.g. 608A) is a stand-aloneprogrammable general purpose computational unit that is capable ofexecuting multiple simultaneous hardware threads while processingmultiple data elements in parallel for each thread. In variousembodiments, the array of execution units 608A-608N is scalable toinclude any number individual execution units.

In some embodiments, the execution units 608A-608N are primarily used toexecute shader programs. A shader processor 602 can process the variousshader programs and dispatch execution threads associated with theshader programs via a thread dispatcher 604. In one embodiment thethread dispatcher includes logic to arbitrate thread initiation requestsfrom the graphics and media pipelines and instantiate the requestedthreads on one or more execution unit in the execution units 608A-608N.For example, the geometry pipeline (e.g., 536 of FIG. 5) can dispatchvertex, tessellation, or geometry shaders to the thread execution logic600 (FIG. 6) for processing. In some embodiments, thread dispatcher 604can also process runtime thread spawning requests from the executingshader programs.

In some embodiments, the execution units 608A-608N support aninstruction set that includes native support for many standard 3Dgraphics shader instructions, such that shader programs from graphicslibraries (e.g., Direct 3D and OpenGL) are executed with a minimaltranslation. The execution units support vertex and geometry processing(e.g., vertex programs, geometry programs, vertex shaders), pixelprocessing (e.g., pixel shaders, fragment shaders) and general-purposeprocessing (e.g., compute and media shaders). Each of the executionunits 608A-608N is capable of multi-issue single instruction multipledata (SIMD) execution and multi-threaded operation enables an efficientexecution environment in the face of higher latency memory accesses.Each hardware thread within each execution unit has a dedicatedhigh-bandwidth register file and associated independent thread-state.Execution is multi-issue per clock to pipelines capable of integer,single and double precision floating point operations, SIMD branchcapability, logical operations, transcendental operations, and othermiscellaneous operations. While waiting for data from memory or one ofthe shared functions, dependency logic within the execution units608A-608N causes a waiting thread to sleep until the requested data hasbeen returned. While the waiting thread is sleeping, hardware resourcesmay be devoted to processing other threads. For example, during a delayassociated with a vertex shader operation, an execution unit can performoperations for a pixel shader, fragment shader, or another type ofshader program, including a different vertex shader.

Each execution unit in execution units 608A-608N operates on arrays ofdata elements. The number of data elements is the “execution size,” orthe number of channels for the instruction. An execution channel is alogical unit of execution for data element access, masking, and flowcontrol within instructions. The number of channels may be independentof the number of physical Arithmetic Logic Units (ALUs) or FloatingPoint Units (FPUs) for a particular graphics processor. In someembodiments, execution units 608A-608N support integer andfloating-point data types.

The execution unit instruction set includes SIMD instructions. Thevarious data elements can be stored as a packed data type in a registerand the execution unit will process the various elements based on thedata size of the elements. For example, when operating on a 256-bit widevector, the 256 bits of the vector are stored in a register and theexecution unit operates on the vector as four separate 64-bit packeddata elements (Quad-Word (QW) size data elements), eight separate 32-bitpacked data elements (Double Word (DW) size data elements), sixteenseparate 16-bit packed data elements (Word (W) size data elements), orthirty-two separate 8-bit data elements (byte (B) size data elements).However, different vector widths and register sizes are possible.

One or more internal instruction caches (e.g., 606) are included in thethread execution logic 600 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,612) are included to cache thread data during thread execution. In someembodiments, a sampler 610 is included to provide texture sampling for3D operations and media sampling for media operations. In someembodiments, sampler 610 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 600 via thread spawningand dispatch logic. Once a group of geometric objects has been processedand rasterized into pixel data, pixel processor logic (e.g., pixelshader logic, fragment shader logic, etc.) within the shader processor602 is invoked to further compute output information and cause resultsto be written to output surfaces (e.g., color buffers, depth buffers,stencil buffers, etc.). In some embodiments, a pixel shader or fragmentshader calculates the values of the various vertex attributes that areto be interpolated across the rasterized object. In some embodiments,pixel processor logic within the shader processor 602 then executes anapplication programming interface (API)-supplied pixel or fragmentshader program. To execute the shader program, the shader processor 602dispatches threads to an execution unit (e.g., 608A) via threaddispatcher 604. In some embodiments, pixel shader 602 uses texturesampling logic in the sampler 610 to access texture data in texture mapsstored in memory. Arithmetic operations on the texture data and theinput geometry data compute pixel color data for each geometricfragment, or discards one or more pixels from further processing.

In some embodiments, the data port 614 provides a memory accessmechanism for the thread execution logic 600 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 614 includes or couples to one or more cachememories (e.g., data cache 612) to cache data for memory access via thedata port.

FIG. 7 is a block diagram illustrating a graphics processor instructionformats 700 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 700 described and illustrated are macro-instructions,in that they are instructions supplied to the execution unit, as opposedto micro-operations resulting from instruction decode once theinstruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit instruction format 710. A 64-bitcompacted instruction format 730 is available for some instructionsbased on the selected instruction, instruction options, and number ofoperands. The native 128-bit instruction format 710 provides access toall instruction options, while some options and operations arerestricted in the 64-bit format 730. The native instructions availablein the 64-bit format 730 vary by embodiment. In some embodiments, theinstruction is compacted in part using a set of index values in an indexfield 713. The execution unit hardware references a set of compactiontables based on the index values and uses the compaction table outputsto reconstruct a native instruction in the 128-bit instruction format710.

For each format, instruction opcode 712 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 714 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). Forinstructions in the 128-bit instruction format 710 an exec-size field716 limits the number of data channels that will be executed inparallel. In some embodiments, exec-size field 716 is not available foruse in the 64-bit compact instruction format 730.

Some execution unit instructions have up to three operands including twosource operands, src0 720, src1 722, and one destination 718. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 724), where the instructionopcode 712 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726 specifying, for example, whether directregister addressing mode or indirect register addressing mode is used.When direct register addressing mode is used, the register address ofone or more operands is directly provided by bits in the instruction.

In some embodiments, the 128-bit instruction format 710 includes anaccess/address mode field 726, which specifies an address mode and/or anaccess mode for the instruction. In one embodiment the access mode isused to define a data access alignment for the instruction. Someembodiments support access modes including a 16-byte aligned access modeand a 1-byte aligned access mode, where the byte alignment of the accessmode determines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction may use 16-byte-aligned addressing for all sourceand destination operands.

In one embodiment, the address mode portion of the access/address modefield 726 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction directly provide the register address of one or moreoperands. When indirect register addressing mode is used, the registeraddress of one or more operands may be computed based on an addressregister value and an address immediate field in the instruction.

In some embodiments instructions are grouped based on opcode 712bit-fields to simplify Opcode decode 740. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 742 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 742 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 744 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 746 includes amix of instructions, including synchronization instructions (e.g., wait,send) in the form of 0011xxxxb (e.g., 0x30). A parallel math instructiongroup 748 includes component-wise arithmetic instructions (e.g., add,multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel mathgroup 748 performs the arithmetic operations in parallel across datachannels. The vector math group 750 includes arithmetic instructions(e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math groupperforms arithmetic such as dot product calculations on vector operands.

Graphics Pipeline

FIG. 8 is a block diagram of another embodiment of a graphics processor800. Elements of FIG. 8 having the same reference numbers (or names) asthe elements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, graphics processor 800 includes a graphics pipeline820, a media pipeline 830, a display engine 840, thread execution logic850, and a render output pipeline 870. In some embodiments, graphicsprocessor 800 is a graphics processor within a multi-core processingsystem that includes one or more general purpose processing cores. Thegraphics processor is controlled by register writes to one or morecontrol registers (not shown) or via commands issued to graphicsprocessor 800 via a ring interconnect 802. In some embodiments, ringinterconnect 802 couples graphics processor 800 to other processingcomponents, such as other graphics processors or general-purposeprocessors. Commands from ring interconnect 802 are interpreted by acommand streamer 803, which supplies instructions to individualcomponents of graphics pipeline 820 or media pipeline 830.

In some embodiments, command streamer 803 directs the operation of avertex fetcher 805 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 803. In someembodiments, vertex fetcher 805 provides vertex data to a vertex shader807, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 805 andvertex shader 807 execute vertex-processing instructions by dispatchingexecution threads to execution units 852A-852B via a thread dispatcher831.

In some embodiments, execution units 852A-852B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 852A-852B have anattached L1 cache 851 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 820 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 811 configures thetessellation operations. A programmable domain shader 817 providesback-end evaluation of tessellation output. A tessellator 813 operatesat the direction of hull shader 811 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 820. Insome embodiments, if tessellation is not used, tessellation components(e.g., hull shader 811, tessellator 813, and domain shader 817) can bebypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 819 via one or more threads dispatched to executionunits 852A-852B, or can proceed directly to the clipper 829. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader819 receives input from the vertex shader 807. In some embodiments,geometry shader 819 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 829 processes vertex data. The clipper829 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer and depth test component 873 in the render output pipeline870 dispatches pixel shaders to convert the geometric objects into theirper pixel representations. In some embodiments, pixel shader logic isincluded in thread execution logic 850. In some embodiments, anapplication can bypass the rasterizer and depth test component 873 andaccess un-rasterized vertex data via a stream out unit 823.

The graphics processor 800 has an interconnect bus, interconnect fabric,or some other interconnect mechanism that allows data and messagepassing amongst the major components of the processor. In someembodiments, execution units 852A-852B and associated cache(s) 851,texture and media sampler 854, and texture/sampler cache 858interconnect via a data port 856 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 854, caches 851, 858 and execution units852A-852B each have separate memory access paths.

In some embodiments, render output pipeline 870 contains a rasterizerand depth test component 873 that converts vertex-based objects into anassociated pixel-based representation. In some embodiments, therasterizer logic includes a windower/masker unit to perform fixedfunction triangle and line rasterization. An associated render cache 878and depth cache 879 are also available in some embodiments. A pixeloperations component 877 performs pixel-based operations on the data,though in some instances, pixel operations associated with 2D operations(e.g. bit block image transfers with blending) are performed by the 2Dengine 841, or substituted at display time by the display controller 843using overlay display planes. In some embodiments, a shared L3 cache 875is available to all graphics components, allowing the sharing of datawithout the use of main system memory.

In some embodiments, graphics processor media pipeline 830 includes amedia engine 837 and a video front end 834. In some embodiments, videofront end 834 receives pipeline commands from the command streamer 803.In some embodiments, media pipeline 830 includes a separate commandstreamer. In some embodiments, video front-end 834 processes mediacommands before sending the command to the media engine 837. In someembodiments, media engine 837 includes thread spawning functionality tospawn threads for dispatch to thread execution logic 850 via threaddispatcher 831.

In some embodiments, graphics processor 800 includes a display engine840. In some embodiments, display engine 840 is external to processor800 and couples with the graphics processor via the ring interconnect802, or some other interconnect bus or fabric. In some embodiments,display engine 840 includes a 2D engine 841 and a display controller843. In some embodiments, display engine 840 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 843 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 820 and media pipeline 830 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL), Open Computing Language (OpenCL),and/or Vulkan graphics and compute API, all from the Khronos Group. Insome embodiments, support may also be provided for the Direct3D libraryfrom the Microsoft Corporation. In some embodiments, a combination ofthese libraries may be supported. Support may also be provided for theOpen Source Computer Vision Library (OpenCV). A future API with acompatible 3D pipeline would also be supported if a mapping can be madefrom the pipeline of the future API to the pipeline of the graphicsprocessor.

Graphics Pipeline Programming

FIG. 9A is a block diagram illustrating a graphics processor commandformat 900 according to some embodiments. FIG. 9B is a block diagramillustrating a graphics processor command sequence 910 according to anembodiment. The solid lined boxes in FIG. 9A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 900 of FIG. 9A includes data fields to identify a targetclient 902 of the command, a command operation code (opcode) 904, andthe relevant data 906 for the command. A sub-opcode 905 and a commandsize 908 are also included in some commands.

In some embodiments, client 902 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 904 and, if present, sub-opcode 905 to determine theoperation to perform. The client unit performs the command usinginformation in data field 906. For some commands an explicit commandsize 908 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 9B shows an exemplary graphics processorcommand sequence 910. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 910 maybegin with a pipeline flush command 912 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 922 and the media pipeline 924 do notoperate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 912 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 913 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 913 isrequired only once within an execution context before issuing pipelinecommands unless the context is to issue commands for both pipelines. Insome embodiments, a pipeline flush command 912 is required immediatelybefore a pipeline switch via the pipeline select command 913.

In some embodiments, a pipeline control command 914 configures agraphics pipeline for operation and is used to program the 3D pipeline922 and the media pipeline 924. In some embodiments, pipeline controlcommand 914 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 914 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 916 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 916 includes selecting the size and number of returnbuffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 920,the command sequence is tailored to the 3D pipeline 922 beginning withthe 3D pipeline state 930 or the media pipeline 924 beginning at themedia pipeline state 940.

The commands to configure the 3D pipeline state 930 include 3D statesetting commands for vertex buffer state, vertex element state, constantcolor state, depth buffer state, and other state variables that are tobe configured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based on the particular3D API in use. In some embodiments, 3D pipeline state 930 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 932 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 932 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 932command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 932 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 922 dispatches shader execution threads to graphicsprocessor execution units.

In some embodiments, 3D pipeline 922 is triggered via an execute 934command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment, commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 910 followsthe media pipeline 924 path when performing media operations. Ingeneral, the specific use and manner of programming for the mediapipeline 924 depends on the media or compute operations to be performed.Specific media decode operations may be offloaded to the media pipelineduring media decode. In some embodiments, the media pipeline can also bebypassed and media decode can be performed in whole or in part usingresources provided by one or more general purpose processing cores. Inone embodiment, the media pipeline also includes elements forgeneral-purpose graphics processor unit (GPGPU) operations, where thegraphics processor is used to perform SIMD vector operations usingcomputational shader programs that are not explicitly related to therendering of graphics primitives.

In some embodiments, media pipeline 924 is configured in a similarmanner as the 3D pipeline 922. A set of commands to configure the mediapipeline state 940 are dispatched or placed into a command queue beforethe media object commands 942. In some embodiments, media pipeline statecommands 940 include data to configure the media pipeline elements thatwill be used to process the media objects. This includes data toconfigure the video decode and video encode logic within the mediapipeline, such as encode or decode format. In some embodiments, mediapipeline state commands 940 also support the use of one or more pointersto “indirect” state elements that contain a batch of state settings.

In some embodiments, media object commands 942 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 942. Once the pipeline state is configured andmedia object commands 942 are queued, the media pipeline 924 istriggered via an execute command 944 or an equivalent execute event(e.g., register write). Output from media pipeline 924 may then be postprocessed by operations provided by the 3D pipeline 922 or the mediapipeline 924. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 10 illustrates exemplary graphics software architecture for a dataprocessing system 1000 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application1010, an operating system 1020, and at least one processor 1030. In someembodiments, processor 1030 includes a graphics processor 1032 and oneor more general-purpose processor core(s) 1034. The graphics application1010 and operating system 1020 each execute in the system memory 1050 ofthe data processing system.

In some embodiments, 3D graphics application 1010 contains one or moreshader programs including shader instructions 1012. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 1014 in a machinelanguage suitable for execution by the general-purpose processor core1034. The application also includes graphics objects 1016 defined byvertex data.

In some embodiments, operating system 1020 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. The operating system 1020 can support agraphics API 1022 such as the Direct3D API, the OpenGL API, or theVulkan API. When the Direct3D API is in use, the operating system 1020uses a front-end shader compiler 1024 to compile any shader instructions1012 in HLSL into a lower-level shader language. The compilation may bea just-in-time (JIT) compilation or the application can perform shaderpre-compilation. In some embodiments, high-level shaders are compiledinto low-level shaders during the compilation of the 3D graphicsapplication 1010. In some embodiments, the shader instructions 1012 areprovided in an intermediate form, such as a version of the StandardPortable Intermediate Representation (SPIR) used by the Vulkan API.

In some embodiments, user mode graphics driver 1026 contains a back-endshader compiler 1027 to convert the shader instructions 1012 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 1012 in the GLSL high-level language are passed to a usermode graphics driver 1026 for compilation. In some embodiments, usermode graphics driver 1026 uses operating system kernel mode functions1028 to communicate with a kernel mode graphics driver 1029. In someembodiments, kernel mode graphics driver 1029 communicates with graphicsprocessor 1032 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 11 is a block diagram illustrating an IP core development system1100 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system1100 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility1130 can generate a software simulation 1110 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation1110 can be used to design, test, and verify the behavior of the IP coreusing a simulation model 1112. The simulation model 1112 may includefunctional, behavioral, and/or timing simulations. A register transferlevel (RTL) design 1115 can then be created or synthesized from thesimulation model 1112. The RTL design 1115 is an abstraction of thebehavior of the integrated circuit that models the flow of digitalsignals between hardware registers, including the associated logicperformed using the modeled digital signals. In addition to an RTLdesign 1115, lower-level designs at the logic level or transistor levelmay also be created, designed, or synthesized. Thus, the particulardetails of the initial design and simulation may vary.

The RTL design 1115 or equivalent may be further synthesized by thedesign facility into a hardware model 1120, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 1165 using non-volatile memory 1140 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 1150 or wireless connection 1160. Thefabrication facility 1165 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

Exemplary System on a Chip Integrated Circuit

FIGS. 12-14 illustrated exemplary integrated circuits and associatedgraphics processors that may be fabricated using one or more IP cores,according to various embodiments described herein. In addition to whatis illustrated, other logic and circuits may be included, includingadditional graphics processors/cores, peripheral interface controllers,or general purpose processor cores.

FIG. 12 is a block diagram illustrating an exemplary system on a chipintegrated circuit 1200 that may be fabricated using one or more IPcores, according to an embodiment. Exemplary integrated circuit 1200includes one or more application processor(s) 1205 (e.g., CPUs), atleast one graphics processor 1210, and may additionally include an imageprocessor 1215 and/or a video processor 1220, any of which may be amodular IP core from the same or multiple different design facilities.Integrated circuit 1200 includes peripheral or bus logic including a USBcontroller 1225, UART controller 1230, an SPI/SDIO controller 1235, andan I²S/I²C controller 1240. Additionally, the integrated circuit caninclude a display device 1245 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 1250 and a mobileindustry processor interface (MIPI) display interface 1255. Storage maybe provided by a flash memory subsystem 1260 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 1265 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine1270.

FIG. 13 is a block diagram illustrating an exemplary graphics processor1310 of a system on a chip integrated circuit that may be fabricatedusing one or more IP cores, according to an embodiment. Graphicsprocessor 1310 can be a variant of the graphics processor 1210 of FIG.12. Graphics processor 1310 includes a vertex processor 1305 and one ormore fragment processor(s) 1315A1315N (e.g., 1315A, 1315B, 1315C, 1315D,through 1315N-1, and 1315N). Graphics processor 1310 can executedifferent shader programs via separate logic, such that the vertexprocessor 1305 is optimized to execute operations for vertex shaderprograms, while the one or more fragment processor(s) 1315A-1315Nexecute fragment (e.g., pixel) shading operations for fragment or pixelshader programs. The vertex processor 1305 performs the vertexprocessing stage of the 3D graphics pipeline and generates primitivesand vertex data. The fragment processor(s) 1315A-1315N use the primitiveand vertex data generated by the vertex processor 1305 to produce aframebuffer that is displayed on a display device. In one embodiment,the fragment processor(s) 1315A-1315N are optimized to execute fragmentshader programs as provided for in the OpenGL API, which may be used toperform similar operations as a pixel shader program as provided for inthe Direct 3D API.

Graphics processor 1310 additionally includes one or more memorymanagement units (MMUs) 1320A-1320B, cache(s) 1325A-1325B, and circuitinterconnect(s) 1330A-1330B. The one or more MMU(s) 1320A-1320B providefor virtual to physical address mapping for integrated circuit 1310,including for the vertex processor 1305 and/or fragment processor(s)1315A-1315N, which may reference vertex or image/texture data stored inmemory, in addition to vertex or image/texture data stored in the one ormore cache(s) 1325A-1325B. In one embodiment the one or more MMU(s)1325A-1325B may be synchronized with other MMUs within the system,including one or more MMUs associated with the one or more applicationprocessor(s) 1205, image processor 1215, and/or video processor 1220 ofFIG. 12, such that each processor 1205-1220 can participate in a sharedor unified virtual memory system. The one or more circuitinterconnect(s) 1330A-1330B enable graphics processor 1310 to interfacewith other IP cores within the SoC, either via an internal bus of theSoC or via a direct connection, according to embodiments.

FIG. 14 is a block diagram illustrating an additional exemplary graphicsprocessor 1410 of a system on a chip integrated circuit that may befabricated using one or more IP cores, according to an embodiment.Graphics processor 1410 can be a variant of the graphics processor 1210of FIG. 12. Graphics processor 1410 includes the one or more MMU(s)1320A-1320B, caches 1325A-1325B, and circuit interconnects 1330A-1330Bof the integrated circuit 1300 of FIG. 13.

Graphics processor 1410 includes one or more shader core(s) 1415A-1415N(e.g., 1415A, 1415B, 1415C, 1415D, 1415E, 1415F, through 1315N-1, and1315N), which provides for a unified shader core architecture in which asingle core or type or core can execute all types of programmable shadercode, including shader program code to implement vertex shaders,fragment shaders, and/or compute shaders. The exact number of shadercores present can vary among embodiments and implementations.Additionally, graphics processor 1410 includes an inter-core taskmanager 1405, which acts as a thread dispatcher to dispatch executionthreads to one or more shader cores 1415A-1415N and a tiling unit 1418to accelerate tiling operations for tile-based rendering, in whichrendering operations for a scene are subdivided in image space, forexample to exploit local spatial coherence within a scene or to optimizeuse of internal caches.

As mentioned above, two sets of possible metadata are utilized in someembodiments. Moreover, the minimum and maximum stencil values of aper-sample data chunk may be used to perform coarse stencil testing, andmay very effectively answer many tests. The bitwise intersection andunion metadata does not degrade in information quality when stencilmasks are employed. A hierarchical stencil testing (as further discussedbelow) may, therefore, be more effective in these cases (e.g., withfewer “ambiguous” results necessitating per-sample tests). Inparticular, hierarchical “equal” and “not equal” tests may be optimal,even with stencil masks. Also, computing the bitwise intersection andunion of stencil values is cheaper (in terms of gates, area, power) thancomputing the minimum and maximum of stencil values.

Compiler-Based Instruction Scoreboarding

To reduce the overhead of a traditional register scoreboard, the subjectmatter described herein implements a solution that utilizes the compilerto enforce data dependencies between instruction executions througheither code scheduling or introducing delays without hardware assistancefor an in-order issue GPU. When the compiler cannot safely satisfy datahazards, hardware can employ an instruction-oriented scoreboard, whichis more area-efficient than a register-based mechanism.

From the point of view of the compiler, not all dependences need be keptduring code execution in an in-order issue execution unit (EU). First,in most instances, if the execution distance (i.e., the amount of timewhich elapses) between two instructions is far enough, there is no needto keep the dependence between the instructions. Since the instructionsare issued in-order and take fixed cycles, if the issue time differenceof these two instructions is longer than the execution time of the firstinstruction, there is no need to keep dependence for the secondinstruction. Second, as the instructions are executed in order, once aninstruction is stalled due to data dependency, all subsequentinstructions will also be blocked for issuing. This stall providesimplicit dependences for the instructions which depend on the sameprevious instruction. As a result, only the latest dependence need betracked to avoid the data hazards.

FIGS. 15 and 16 illustrate dependence between instructions in accordancewith some examples. By way of example, in FIG. 15 the execution time ofinstruction 1 is 14 cycles, and instruction 30 depends on instruction 1.In this case, there is no need to track dependency between the pairbecause the issuing of instructions 2 to 29 will take longer than 14cycles. In FIG. 16, instructions 2 and 7 depend on instruction 1 andinstruction 2 is executed before instruction 7. In this situation, thereis no need to track dependency between instructions 1 and 7, as in-orderissue means that instruction 7 will not be executed if instruction 2 isstalled due to the dependence caused by register r1.

Described herein is an explicit instruction scoreboard mechanism. In thehardware, an instruction oriented scoreboard array is adapted for eachhardware thread of the execution unit (EU). Each element in the array isused as a scoreboard item and can be referenced through its index. Atthe same time, each instruction is extended with two fields: a defineindex and a use index, which may be used to index into the scoreboard.

In order issue doesn't guarantee the results of instructions will becommitted in-order. When an instruction depends on multiple previousinstructions, it has to wait for all of the results to be committed. Theinstruction scoreboard supports this functionality by providing acounter for each scoreboard element. Each counter is initialized tozero. When an instruction is issued, the scoreboard counter specified bythe define index is incremented by one. When the instruction completesthe scoreboard counter is decrements by one. An instruction can beexecuted only when counter specified by use index is zero.

The hardware instruction scoreboard size can be bounded by the cyclesrequired by the instruction issue and the pipeline execution. Forexample, assume an arithmetic logic unit (ALU) instruction takes twocycles to issue and at most thirty cycles to complete. In that case,sixteen scoreboard entries are sufficient to capture all the dependencesrequired to avoid the data hazard. The size of scoreboard counter issimilarly limited by the maximum number of in-flight instructions, sofour bits are sufficient for a counter to capture all the dependenciesthat one instruction may have.

FIG. 17 is a schematic illustration of how a scoreboard counter works inaccordance with some examples. In the example depicted in FIG. 17,instruction 4 depends on instructions 1, 2, 3. The scoreboard counter 0is assigned to those instructions to track the multiple dependences. Thecounter increases when instruction 1, 2 and 3 are issued and decreaseswhen instructions 1, 2 and 3 are committed. The execution of instruction4 is delayed until all previous instructions are committed and thecounter's value is cleared to 0.

The execution latency of memory instructions may be unbounded (e.g., dueto page faults). However, some architectures have the limitation on themaximum number (e.g., 32) outstanding memory load instructions per EUthat can be in the execution state at the same time. In sucharchitectures the per-thread instruction scoreboard can be extended witheight more entries to improve the dependency tracking capability formemory load instructions. Two considerations are behind this. First,most general instructions take between 14 and 22 execution cycles exceptfor floating-point div( ) and pow( ) instructions. Thus, 11 scoreboarditems are sufficient for most general instructions, leaving 13 items formemory load instructions. Second, in the worst case that there are notenough scoreboard items to satisfy the all the dependence trackingrequirements, the compiler can be conservative in its instructionscoreboard assignment at the expense of some false dependencies.

The compiler is used to allocate the scoreboard items for eachinstruction. During the compilation process, the scoreboard allocationis executed after instruction scheduling so that the data dependencegraph (DDG) built during scheduling can be reused. FIG. 18 is a flowdiagram illustrating scoreboarding operations according to someembodiments.

The first step is to simplify the DDG by removing unnecessary dependenceedges along the instruction execution paths. Referring first to FIG. 18in some examples logic which executes in a compiler may, at operation1810, determine a distance (i.e., the amount of time which elapses)between a source node instruction and one or more destination nodeinstructions.

At operation 1815 logic which executes in the compiler may remove adependence edge between the source node instruction and a destinationnode instruction when a product of the distance between the source nodeinstruction and the destination node instruction and the instructionissue cycle is greater than an execution cycle of the source nodeinstruction. Similarly, as shown in FIG. 16, if multiple instructionsdepend on one instruction cases, only the edge for the latest one iskept.

At operation 1820 logic which executes in the compiler may partition theDDG into sub-graphs according to merge and branch edges. In the DDG,merge and branch edges represent the dependence scenarios that oneinstruction depends on multiple previous instructions and multipleinstructions depend on one instruction. After separating these two kindsof sub-graphs, in the remaining DDG graph, the connected edges aregrouped together and also classified into sub-graphs. The sub-graphclassification is based on the observation that all the edges in the subgraph can share same scoreboard item without generating any falsedependence.

FIG. 19 shows three types of sub-graphs after DDG graph simplification.All edges in the a) merge sub graph can be assigned with same scoreboardcounter. For the b) branch sub graph, dependence edges in differentbranches must across different control flow branches. Because thein-order issue based simplification in first step should eliminated onesin same execution paths. Figure c) gives out the in-order sub graph.Since there is no edge interference between the edges in this graph,same scoreboard item can be assigned to all the edges in it.

At operation 1825 logic which executes in the compiler may determinelive ranges for the sub-graphs defined in operation 1820. In someexamples the live range of a sub-graph is the union of the live rangesof all the dependence edges within the sub-graph.

At operation 1830 logic which executes in the compiler may assignscoreboard entries to the sub-graphs. In some examples, differentscoreboard indices are assigned if there is interference between liveranges for different sub-graph. Based on the live ranges, anytraditional register allocation algorithms like linear scan or graphcoloring can be used here for scoreboard item allocation.

FIG. 20 is a schematic illustration of a scoreboard allocation process,according to examples. An example code piece is depicted in 20(a). FIG.20(b) illustrates the data dependence graph (DDG) between theinstructions in the code depicted in FIG. 20(a). FIG. 20(c) illustratesthe DDG after simplification. Due to in-order issue, the dependent edgesfrom instruction 4 to multiple successors 7, 8, 9 are pruned and onlythe latest edge from 4 to 6 is kept. Also the edge from 3 to 13 isremoved due to the large instruction distance. FIG. 20(d) shows theresult of sub-graph partitioning. Edges (7, 11) (8, 11) are classifiedinto a sub graph, while (3, 5) (5, 8) and are classified to another one.FIGS. 20(e) and 20(f) illustrate the scoreboard allocation result foreach dependence edge after interference-based allocation. From theexample we can see that for the example which original needs 13 registerscoreboard items, only 3 instruction scoreboard items are enough toavoid the data hazard.

The following pertains to further examples.

Example 1 may optionally include an apparatus comprising logic, at leastpartially comprising hardware logic, to remove unnecessary dependenceedges from a data dependency graph; partition the data dependency graphinto a plurality of sub-graphs; determine a live range for each of theplurality of sub-graphs; and assign a scoreboard entry to each of theplurality of sub-graphs, wherein sub-graphs which have interfering liveranges are assigned different scoreboard entries.

Example 2 may optionally include the subject matter of example 1,further comprising logic, at least partially including hardware logic,to determine a distance between a source node instruction and one ormore destination node instructions in the data dependency graph; andremove a dependence edge between the source node instruction and adestination node instruction when a product of the distance between thesource node instruction and the destination node instruction and theinstruction issue cycle is greater than an execution cycle of the sourcenode instruction.

Example 3 may optionally include the subject matter of any one ofexamples 1-2, further comprising logic, at least partially includinghardware logic, to locate a source node instruction on the datadependency graph which includes a plurality of dependence edges; anddelete one or more unnecessary dependence edges from the source nodeinstruction.

Example 4 may optionally include the subject matter of any one ofexamples 1-3, wherein the logic to determine a live range furthercomprising logic, at least partially including hardware logic, todetermine a union of live ranges of all the dependence edges in asubgraph.

Example 5 may optionally include the subject matter of any one ofexamples 1-4, further comprising logic, at least partially includinghardware logic, to associate a counter, with each scoreboard entry; andassociate a define index and a use index with each instruction.

Example 6 may optionally include the subject matter of any one ofexamples 1-5, further comprising logic, at least partially includinghardware logic, to execute an instruction only when the counterspecified by the use index is zero.

Example 7 may optionally include a method comprising removingunnecessary dependence edges from a data dependency graph; partitioningthe data dependency graph into a plurality of sub-graphs; determining alive range for each of the plurality of sub-graphs; and assigning ascoreboard entry to each of the plurality of sub-graphs, whereinsub-graphs which have interfering live ranges are assigned differentscoreboard entries:

Example 8 may optionally include the subject matter of example 7,further comprising determining a distance between a source nodeinstruction and one or more destination node instructions in the datadependency graph; and removing one or more unnecessary dependence edgesbetween the source node a destination node when a product of thedistance between the source node instruction and the destination nodeinstruction and the instruction issue cycle is greater than an executioncycle of the source node instruction.

Example 9 may optionally include the subject matter of any one ofexamples 7-8, further comprising locating source node instruction on thedata dependency graph which includes a plurality of dependence edges;and deleting one or more unnecessary dependence edges from the sourcenode instruction.

Example 10 may optionally include the subject matter of any one ofexamples 7-9 further comprising determining a union of live ranges ofall the dependence edges in a subgraph.

Example 11 may optionally include the subject matter of any one ofexamples 7-10 further comprising associating a counter, with eachscoreboard entry; and associate a define index and a use index with eachinstruction

Example 12 may optionally include the subject matter of any one ofexamples 7-11 wherein executing an instruction only when the counterspecified by the use index is zero.

Example 13 may optionally include one or more computer-readable mediumcomprising one or more instructions that when executed on at least oneprocessor configure the at least one processor to perform one or moreoperations to remove unnecessary dependence edges from a data dependencygraph; partition the data dependency graph into a plurality ofsub-graphs; determine a live range for each of the plurality ofsub-graphs; and assign a scoreboard entry to each of the plurality ofsub-graphs, wherein sub-graphs which have interfering live ranges areassigned different scoreboard entries.

Example 14 may optionally include the subject matter of example 13,further comprising one or more instructions that when executed on the atleast one processor configure the at least one processor to determine adistance between a source node instruction and one or more destinationnode instructions in the data dependency graph; and remove a dependenceedge between the source node a destination node when a product of thedistance between the source node instruction and the destination nodeinstruction and the instruction issue cycle is greater than an executioncycle of the source node instruction.

Example 15 may optionally include the subject matter of any one ofexamples 13-14, further comprising one or more instructions that whenexecuted on the at least one processor configure the at least oneprocessor to locate a source node instruction on the data dependencygraph which includes a plurality of dependence edges; and delete one ormore unnecessary dependence edges from the source node instruction.

Example 16 may optionally include the subject matter of any one ofexamples 13-15, further comprising one or more instructions that whenexecuted on the at least one processor configure the at least oneprocessor to determine a union of live ranges of all the dependenceedges in a subgraph.

Example 17 may optionally include the subject matter of any one ofexamples 13-16, further comprising one or more instructions that whenexecuted on the at least one processor configure the at least oneprocessor to associate a counter, a define index and, a use index witheach scoreboard entry.

Example 18 may optionally include the subject matter of any one ofexamples 13-17, further comprising one or more instructions that whenexecuted on the at least one processor configure the at least oneprocessor to execute an instruction only when the counter specified bythe use index is zero.

Example 19 may optionally include an electronic device, comprising aprocessor having one or more processor cores logic, at least partiallycomprising hardware logic, to remove unnecessary dependence edges from adata dependency graph; partition the data dependency graph into aplurality of sub-graphs; determine a live range for each of theplurality of sub-graphs; and assign a scoreboard entry to each of theplurality of sub-graphs, wherein sub-graphs which have interfering liveranges are assigned different scoreboard entries.

Example 20 may optionally include the subject matter of example 19,further comprising logic, at least partially including hardware logic,to determine a distance between a source node instruction and one ormore destination node instructions in the data dependency graph; andremove a dependence edge between the source node instruction and adestination node instruction when a product of the distance between thesource node instruction and the destination node instruction and theinstruction issue cycle is greater than an execution cycle of the sourcenode instruction.

Example 21 may optionally include the subject matter of any one ofexamples 19-20, further comprising logic, at least partially includinghardware logic, to locate a source node instruction on the datadependency graph which includes a plurality of dependence edges; anddelete one or more unnecessary dependence edges from the source nodeinstruction.

Example 22 may optionally include the subject matter of any one ofexamples 19-21, wherein the logic to determine a live range furthercomprising logic, at least partially including hardware logic, todetermine a union of live ranges of all the dependence edges in asubgraph.

Example 23 may optionally include the subject matter of any one ofexamples 19-22, further comprising logic, at least partially includinghardware logic, to associate a counter, with each scoreboard entry; andassociate a define index and a use index with each instruction.

Example 24 may optionally include the subject matter of any one ofexamples 19-23, further comprising logic, at least partially includinghardware logic, to execute an instruction only when the counterspecified by the use index is zero.

In various embodiments, the operations discussed herein, e.g., withreference to FIGS. 1-18, may be implemented as hardware (e.g., logiccircuitry), software, firmware, or combinations thereof, which may beprovided as a computer program product, e.g., including a tangible(e.g., non-transitory) machine-readable or computer-readable mediumhaving stored thereon instructions (or software procedures) used toprogram a computer to perform a process discussed herein. Themachine-readable medium may include a storage device such as thosediscussed with respect to FIGS. 1-18.

Additionally, such computer-readable media may be downloaded as acomputer program product, wherein the program may be transferred from aremote computer (e.g., a server) to a requesting computer (e.g., aclient) by way of data signals provided in a carrier wave or otherpropagation medium via a communication link (e.g., a bus, a modem, or anetwork connection).

Reference in the specification to “one embodiment” or “an embodiment”means that a particular feature, structure, and/or characteristicdescribed in connection with the embodiment may be included in at leastan implementation. The appearances of the phrase “in one embodiment” invarious places in the specification may or may not be all referring tothe same embodiment.

Also, in the description and claims, the terms “coupled” and“connected,” along with their derivatives, may be used. In someembodiments, “connected” may be used to indicate that two or moreelements are in direct physical or electrical contact with each other.“Coupled” may mean that two or more elements are in direct physical orelectrical contact. However, “coupled” may also mean that two or moreelements may not be in direct contact with each other, but may stillcooperate or interact with each other.

Thus, although embodiments have been described in language specific tostructural features and/or methodological acts, it is to be understoodthat claimed subject matter may not be limited to the specific featuresor acts described. Rather, the specific features and acts are disclosedas sample forms of implementing the claimed subject matter.

The invention claimed is:
 1. An apparatus comprising: a processor to:remove one or more unnecessary dependence edges from a data dependencygraph which represents one or dependencies between instructions forexecution on a processing device; partition the data dependency graphinto a plurality of sub-graphs based on dependence characteristics ofthe instructions for execution; determine a live range for each of theplurality of sub-graphs; and assign a scoreboard entry to each of theplurality of sub-graphs, wherein sub-graphs which have interfering liveranges are assigned different scoreboard indices which identify anexecution order for operations in the plurality of sub-graphs.
 2. Theapparatus of claim 1, the processor to: determine a distance between asource node instruction and one or more destination node instructions inthe data dependency graph; and remove a dependence edge between thesource node instruction and a destination node instruction when aproduct of the distance between the source node instruction and thedestination node instruction and the instruction issue cycle is greaterthan an execution cycle of the source node instruction.
 3. The apparatusof claim 1, the processor to: locate a source node instruction on thedata dependency graph which includes a plurality of dependence edges;and delete one or more unnecessary dependence edges from the source nodeinstruction.
 4. The apparatus of claim 1, the processor to: determine aunion of live ranges of all the dependence edges in a subgraph.
 5. Theapparatus of claim 1, the processor to: associate a counter, with eachscoreboard entry; and associate a define index and a use index with eachinstruction.
 6. The apparatus of claim 5, the processor to: execute aninstruction only when the counter specified by the use index is zero. 7.A method comprising: removing one or more unnecessary dependence edgesfrom a data dependency graph which represents one or dependenciesbetween instructions for execution on a processing device; partitioningthe data dependency graph into a plurality of sub-graphs based ondependence characteristics of the instructions for execution;determining a live range for each of the plurality of sub-graphs; andassigning a scoreboard entry to each of the plurality of sub-graphs,wherein sub-graphs which have interfering live ranges are assigneddifferent scoreboard indices which identify an execution order foroperations in the plurality of sub-graphs.
 8. The method of claim 7,further comprising: determining a distance between a source nodeinstruction and one or more destination node instructions in the datadependency graph; and removing one or more unnecessary dependence edgesbetween the source node instruction and a destination node instructionwhen a product of the distance between the source node instruction andthe destination node instruction and the instruction issue cycle isgreater than an execution cycle of the source node instruction.
 9. Themethod of claim 7, further comprising: locating source node instructionon the data dependency graph which includes a plurality of dependenceedges; and deleting one or more unnecessary dependence edges from thesource node instruction.
 10. The method of claim 7, further comprising:determining a union of live ranges of all the dependence edges in asubgraph.
 11. The method of claim 7 further comprising: associating acounter, with each scoreboard entry; and associating a define index anda use index with each instruction.
 12. The method of claim 11, wherein:executing an instruction only when the counter specified by the useindex is zero.
 13. One or more non-transitory computer-readable mediumcomprising one or more instructions that when executed on at least oneprocessor configure the at least one processor to perform one or moreoperations to: remove one or more unnecessary dependence edges from adata dependency graph which represents one or dependencies betweeninstructions for execution on a processing device; partition the datadependency graph into a plurality of sub-graphs based on dependencecharacteristics of the instructions for execution; determine a liverange for each of the plurality of sub-graphs; and assign a scoreboardentry to each of the plurality of sub-graphs, wherein sub-graphs whichhave interfering live ranges are assigned different scoreboard indiceswhich identify an execution order for operations in the plurality ofsub-graphs.
 14. The non-transitory computer-readable medium of claim 13comprising one or more instructions that when executed on the at leastone processor configure the at least one processor to: determine adistance between a source node instruction and one or more destinationnode instructions in the data dependency graph; and remove a dependenceedge between the source node instruction and a destination nodeinstruction when a product of the distance between the source nodeinstruction and the destination node instruction and the instructionissue cycle is greater than an execution cycle of the source nodeinstruction.
 15. The non-transitory computer-readable medium of claim13, comprising one or more instructions that when executed on the atleast one processor configure the at least one processor to: locate asource node instruction on the data dependency graph which includes aplurality of dependence edges; and delete one or more unnecessarydependence edges from the source node instruction.
 16. Thenon-transitory computer-readable medium of claim 13, comprising one ormore instructions that when executed on the at least one processorconfigure the at least one processor to: determine a union of liveranges of all the dependence edges in a subgraph.
 17. The non-transitorycomputer-readable medium of claim 13, comprising one or moreinstructions that when executed on the at least one processor configurethe at least one processor to: associate a counter, a define index and,a use index with each scoreboard entry.
 18. The non-transitorycomputer-readable medium of claim 17, comprising one or moreinstructions that when executed on the at least one processor configurethe at least one processor to: execute an instruction only when thecounter specified by the use index is zero.
 19. An electronic device,comprising: a processor having one or more processor cores, theprocessor to: remove one or more unnecessary dependence edges from adata dependency graph which represents one or dependencies betweeninstructions for execution on a processing device; partition the datadependency graph into a plurality of sub-graphs based on dependencecharacteristics of the instructions for execution; determine a liverange for each of the plurality of sub-graphs; and assign a scoreboardentry to each of the plurality of sub-graphs, wherein sub-graphs whichhave interfering live ranges are assigned different scoreboard indiceswhich identify an execution order for operations in the plurality ofsub-graphs; and a memory communicatively coupled to the processor. 20.The electronic device of claim 19 the processor to: determine a distancebetween a source node instruction and one or more destination nodeinstructions in the data dependency graph; and remove a dependence edgebetween the source node instruction and a destination node instructionwhen a product of the distance between the source node instruction andthe destination node instruction and the instruction issue cycle isgreater than an execution cycle of the source node instruction.
 21. Theelectronic device of claim 19, the processor to: locate a source nodeinstruction on the data dependency graph which includes a plurality ofdependence edges; and delete at least one dependence edge from thesource node instruction.
 22. The electronic device of claim 19, theprocessor to: determine a union of live ranges of all the dependenceedges in a subgraph.
 23. The electronic device of claim 19, theprocessor to: associate a counter, a define index and, a use index witheach scoreboard entry.
 24. The electronic device of claim 23, theprocessor to: execute an instruction only when the counter specified bythe use index is zero.